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orderin g numbe r : ena1626 bi-cmos ic for digital still cameras single-chip motor driver ic for LV8048CS overview LV8048CS is single-chip motor dr iver ic for digital still cameras. features ? the actuator driver for dsc is built into single-chip. ? two 256-division microstep output channel, and two constant current output channels ? all actuators can be driven at the same time ? af / zoom stepping motor is driven by the clock signal ? supports pwm control of a dc zoom motor ? the constant current output reference voltage can be set to one of 16 internal reference voltage levels (motor holding current switching possible). ? two photosensor drive transistor channels ? two schmitt buffer channels (the presence or absence of hysteresis can be set individually). specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage 1 v b max 6.0 v supply voltage 2 v cc max 6.0 v i o peak1 out5 to 6, out9 to 10 (t 10ms, on-duty 20%) 800 ma peak output curren t i o peak2 out1 to 4, out7 to 8, out11 to 12 (t 10ms, on-duty 20%) 600 ma i o max1 out5 to 6, out9 to 10 600 ma i o max2 out1 to 4, out7 to 8, out11 to 12 400 ma continuous output current i o max3 pi1, pi2 40 ma continued on next page. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. d2409 sy 20091110-s00001 no.a1626-1/28
LV8048CS no.a1626-2/28 continued from preceding page. parameter symbol conditions ratings unit allowable power dissipation pd max mounted on a circuit board* 1100 mw operating temperature topr -20 to +85 c storage temperature tstg -55 to +150 c * specified circuit board : 40 50 0.8mm 3 : glass epoxy four-layer board(2s-2p). recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage range 1 v b vb1, vb2 (*1) (*2) 2.7 to 5.5 v supply voltage range 2 v cc (*2) 2.7 to 5.5 v logic level input voltage v in 0 to v cc +0.3 v clock frequency f clk clk1, clk2/pwm, clk3/ena6 to 64 khz pwm frequency f pwm clk2/pwm to 100 khz (*1) there are no restrictions on the magnitude rela tionships between the voltages applied to vb1 and vb2. (*2) there are no restrictions on the magnitude relationships between the voltages applied to each v b and v cc . electrical characteristics at ta = 25c, v b = 5v, v cc = 3.3v ratings parameter symbol conditions min typ max unit quiescent current i cco st = low, bi1, bi2 = low 1 a current drain 1 i b st = high, bi1, bi2 = low, with no output load 75 150 a current drain 2 i cc st = high, bi1, bi2 = low, with no output load 2.5 4 ma v cc low-voltage cutoff voltage v th v cc 2.1 2.4 2.6 v low-voltage hysteresis voltage v th hys 90 140 190 mv thermal shutdown temperature tsd design target value 160 180 200 c thermal hysteresis width tsd design target value 20 40 60 c af/zoom motor drivers (out1-2, out3-4, out5-6, out7-8) ronu1 i o = 200ma, high side on-resistance 0.6 0.85 output on-resistance 1 rond1 i o = 200ma, low side on-resistance 0.25 0.4 output leakage current 1 i o leak1 1 a diode forward voltage 1 v d 1 i d = -400ma 0.7 0.9 1.2 v fchop1 293 390 488 khz fchop2 146 195 244 khz fchop3 428 570 713 khz chopping frequency fchop4 214 285 356 khz vsen00 0.185 0.200 0.215 v vsen01 0.125 0.140 0.155 v vsen10 0.085 0.100 0.115 v current setting reference voltage vsen11 0.045 0.060 0.075 v i in l v in = 0v (st, clk1, clk2/pwm) 1.0 a logic pin input current i in h v in = 3.3v (st, clk1, clk2/pwm) 33 50 a high-level input voltage v in h st, clk1, clk2/pwm 2.5 v low-level input voltage v in l st, clk1, clk2/pwm 1.0 v motor driver for aperture, shutter (out9-10, out11-12) ronu2 i o = 200ma, high side on-resistance 0.6 0.85 output on-resistance 2 rond2 i o = 200ma, low side on-resistance 0.25 0.4 output leakage current 2 i o leak2 1 a diode forward voltage 2 v d 2 i d = -400ma 0.7 0.9 1.2 v constant current output i o rf = 1 , (d3, d4, d5, d6) = (0, 0, 0, 0) 190 200 210 ma continued on next page.
LV8048CS continued from preceding page. ratings parameter symbol conditions min typ max unit v ref 1 (d3, d4, d5, d6) = (0, 0, 0, 0) 0.190 0.200 0.210 v v ref 2 (d3, d4, d5, d6) = (1, 0, 0, 0) 0.162 0.170 0.179 v v ref 3 (d3, d4, d5, d6) = (0, 1, 0, 0) 0.157 0.165 0.173 v v ref 4 (d3, d4, d5, d6) = (1, 1, 0, 0) 0.152 0.160 0.168 v v ref 5 (d3, d4, d5, d6) = (0, 0, 1, 0) 0.147 0.155 0.163 v v ref 6 (d3, d4, d5, d6) = (1, 0, 1, 0) 0.143 0.150 0.158 v v ref 7 (d3, d4, d5, d6) = (0, 1, 1, 0) 0.138 0.145 0.152 v v ref 8 (d3, d4, d5, d6) = (1, 1, 1, 0) 0.133 0.140 0.147 v v ref 9 (d3, d4, d5, d6) = (0, 0, 0, 1) 0.128 0.135 0.142 v v ref 10 (d3, d4, d5, d6) = (1, 0, 0, 1) 0.124 0.130 0.137 v v ref 11 (d3, d4, d5, d6) = (0, 1, 0, 1) 0.119 0.125 0.131 v v ref 12 (d3, d4, d5, d6) = (1, 1, 0, 1) 0.114 0.120 0.126 v v ref 13 (d3, d4, d5, d6) = (0, 0, 1, 1) 0.109 0.115 0.121 v v ref 14 (d3, d4, d5, d6) = (1, 0, 1, 1) 0.105 0.110 0.116 v v ref 15 (d3, d4, d5, d6) = (0, 1, 1, 1) 0.100 0.105 0.110 v internal current setting reference voltages v ref 16 (d3, d4, d5, d6) = (1, 1, 1, 1) 0.095 0.100 0.105 v motor holding drive switching rate rhold 33 % i in l v in = 0v (clk3/ena6) 1.0 a logic pin input current i in h v in = 3.3v (clk3/ena6) 33 50 a high-level input voltage v in h clk3/ena6 2.5 v low-level input voltage v in l clk3/ena6 1.0 v photosensor peripheral circuits (p i1, pi2, bi1, bo1, bi2, bo2) ron3a i o = 20ma, pi1, pi2 2.4 5 output on-resistance 3 ron3b i o = 40ma, pi1, pi2 2.4 5 output leakage current 3 i o leak3 pi1, pi2 1 a v th h 1.00 1.28 1.50 v schmitt buffer threshold level (hysteresis) v th l 0.60 0.84 1.10 v schmitt buffer hysteresis v th hys1 0.3 0.44 0.6 v schmitt buffer threshold level (no hysteresis) v th 0.90 1.20 1.40 v serial data transfer pins i in l v in = 0v (sclk, data, stb) 1.0 a logic pin input current i in h v in = 3.3v (sclk, data, stb) 33 50 a high-level input voltage v in h sclk, data, stb 2.5 v low-level input voltage v in l sclk, data, stb 1.0 v minimum sclk high-level pulse width tsch 0.125 s minimum sclk low-level pulse width tscl 0.125 s stipulated stb time tlat 0.125 s minimum stb pulse width tlatw 0.125 s data setup time tds 0.125 s data hold time tdh 0.125 s maximum clk frequency fclk 4 mhz tsch sclk data stb tscl fclk tds tdh d0 d1 d2 d7 d8 tlat tlatw no.a1626-3/28
LV8048CS package dimensions unit : mm (typ) 3389 sanyo : wlp36(2.87x2.47) top view side view side view bottom view 0.245 fedcba 0.65 max 0.175 2.47 2.87 0.4 0.235 1234567 0.235 0.4 pd max -- ta 1.6 0 100 -20 1.2 1.10 0.8 0.4 80 60 40 20 0 0.57 85 ambient temperature, ta -- c allowable power dissipation, pd max -- w specified substrate: 40 500.8mm 3 glass epoxy four-layer board. pin assignment no.a1626-4/28 rf6 out11 out8 out12 bi2 bi1 rf4 bo1 out7 pi2 out6 pi1 rf3 out5 bo2 sgnd v cc pgnd clk3 /ena6 out2 out1 rf1 clk2 /pwm clk1 out4 rf2 st out3 stb rf5 sclk vb2 data vb1 out9 out10 1 2 3 4 5 6 7 f e d c b a rf6 out11 out8 out12 bi2 bi1 rf4 bo1 out7 pi2 out6 pi1 rf3 out5 bo2 sgnd v cc pgnd clk3 /ena6 out2 out1 rf1 clk2 /pwm clk1 out4 rf2 st out3 stb rf5 sclk vb2 data vb1 out9 out10 1 2 3 4 5 6 7 f e d c b a bottom view top view
LV8048CS block diagram cpu out12 out11 rf5 out10 out9 rf4 out4 out3 out2 out1 rf3 clk2 /pwm bi1 clk1 st sgnd v cc sclk data stb clk3 /ena6 pi1 pi2 bo1 bi2 bo2 v cc 40ma max rf2 vb1 rf1 rf6 + - + - + - + - + - + - 40ma max + - + - vb2 out5 out6 out7 out8 pgnd to an asic vb1 vb2 no.a1626-5/28 microstep microstep constant current constant current output control logic output control logic logic/pre-drive circuit logic/pre-drive circuit reference voltage circuit excitation signal generator (2 phase/1-2 phase) thermal protection circuit reference voltage selection (0.1 to 0.2v in 16 steps) reference voltage selection (0.1 to 0.2v in 16 steps) serial-parallel converter (9 bits) current selection (microstep, 1-2 phase, 1-2 phase full torque or 2 phase mode) current selection (microstep, 1-2 phase, 1-2 phase full torque or 2 phase mode) excitation signal generation circuit (microstep, 1-2 phase, 1-2 phase full torque or 2 phase mode) oscillation circuit current selection (microstep, 1-2 phase, 1-2 phase full torque or 2 phase mode) current selection (microstep, 1-2 phase, 1-2 phase full torque or 2 phase mode) excitation signal generation circuit (microstep, 1-2 phase, 1-2 phase full torque or 2 phase mode) microstep microstep
LV8048CS no.a1626-6/28 pin functions pin no. pin name description c1 vb1 power supply for out1-4, out9-10 d1 vb2 power supply for out5-8, out11-12 c7 pgnd power system ground c6 v cc control system power supply d7 sgnd control system ground a6 out1 motor driver output b7 out2 motor driver output a3 out3 motor driver output a5 out4 motor driver output e1 out5 motor driver output f2 out6 motor driver output f3 out7 motor driver output f5 out8 motor driver output b1 out9 motor driver output a2 out10 motor driver output f6 out11 motor driver output e7 out12 motor driver output a7 rf1 current detection connection for out1-2 a4 rf2 current detection connection for out3-4 f1 rf3 current detection connection for out5-6 f4 rf4 current detection connection for out7-8 a1 rf5 current detection connection for out9-10 f7 rf6 current detection connection for out11-12 e2 pi1 photosensor drive output e3 pi2 photosensor drive output e5 bi1 schmitt buffer input 1 e4 bo1 schmitt buffer output 1 e6 bi2 schmitt buffer input 2 d6 bo2 schmitt buffer output 2 b3 st chip enable d2 sclk serial data transfer clock c2 data serial data b2 stb serial data latch pulse input b4 clk1 stepping motor clock for out1-4 b5 clk2/pwm stepping motor clock for out5-8/p wm input for out5-8/pwm input for out9-10 b6 clk3/ena6 stepping motor clock for out9-12/enable input for out11-12
LV8048CS serial data input overview serial data input timing chart d0 data sclk stb st d1 d2 d3 d4 d5 d6 d7 d8 this edge latches the state setting data. data is input in order from d0 to d8. data is transferred on the sclk rising edge and, after all data has been transferred, the data is latched by the rising edge of the stb signal. note that the ic internal circuits will not accep t the sclk signal while the stb signal is high. timing with which the serial data is reflected in the outputs basically, the new values are reflected in the output at the point the data is latched with the stb signal. pattern 1 however, the "excitation direction" and "excitation mode" settings used in stepping motor clock drive mode for channels 1 through 4 are an excep tion. in this case only, after the data is la tched with the stb signal, the new values are reflected on the next rising edge of the clk1 signal and clk2 signal. pattern 2 (similarly, the ?excitation direction? and ?excitation ?mode settings used in the stepping motor clock drive mode for channels 5 to 6 are also an exception. after the data is latc hed with the stb signal, the ne w values are reflected on the next rising edge of the clk3 signal.) [pattern 1] [pattern 2] clk stb data latch timing data latch timing rising edge timing stb timing clk stb no.a1626-7/28
LV8048CS no.a1626-8/28 detailed description of serial data input note: this ic's channels are assigned as follows. out1/out2 channel 1 out3/out4 channel 2 out5/out6 channel 3 out7/out8 channel 4 out9/out10 channel 5 out11/out12 channel 6 stepping motor excitation type for channels 1 through 6 this ic supports connecting stepping motors to channels 1 and 2 and 3 and 4 to channels 5 and 6. either of these stepping motors can be controlled by a single clock signal. when this capability is used, the clock signal input pi ns and the channels as associated as shown below. clk1 : controls channel 1 and 2 drive clk2/pwm : controls channel 3 and 4 drive clk3/ena6 : controls channel 5 and 6 drive the following state settings related to control of these steppi ng motors are set using the serial data. (see subsection, serial logic table 1, 2, in section ,truth tables, for a detailed description of this data.) [for channel 1 to 4 drive] excitation mode : 2-phase, 1-2 phase (full torque), 1-2 phase or microstep microstep division number : 256 or 128 excitation direction : cw (clockwise) or ccw (counterclockwise) step/hold : clear or hold counter reset: clear or reset output enable : output off or output on chopping frequency : selects one of four values current setting reference voltage : selects one of four values [for channel 5, 6 drive] excitation mode : 2-phase, 1-2 phase excitation direction : cw (clockwise) or ccw (counterclockwise) step/hold : clear or hold counter reset : clear or reset output enable : output off or output on
LV8048CS [clk1] pin function input st clk1 operational mode l * standby mode h excitation step sending h excitation step maintenance [clk2/pwm] possession [clk3/ena6] similar excitation mode setting : (d0 = [1], d1 = [0], d2 = [0], d3 = [0]) ? d4 d5 d6 excitation mode 1ch 2ch 0 0 * 2-phase 100% -100% 1 0 * 1-2 phase (full torque) 100% 0% 0 1 * 1-2 phase 100% 0% 0 microstep (256step) 1 1 1 microstep (128step) 100% 0% it is an initial position in e ach excitation mode when the counter is reset th e state in the early st arting up the power supply . the serial data for standard voltage setting : (d0 = [0], d1 = [1], d2 = [1], d3 = [0]) d6 d7 current setting and standard voltages 0 0 0.2v 1 0 0.140v 0 1 0.1v 1 1 0.060v a standard voltage for the current the setting and the standard voltage output current setting can be switched to four stages by the serial data. it is effective for the power saving when the motor energizes maintenance. (computational method of set current value) a standard voltage can set the output current from the rf resistance connected between standard voltage and terminal rf-gnd because it is changeability can (0 .2v,0.140v,0.1v,0.060v) in the serial data. i out = (standard voltage x set current ratio) / rf resistance (example)the following output current flows in 100% and the rf resistance 1 ? compared with 0.2v in a standard voltage and set currents at times. i out = 0.2v 100% / 1 ? = 200ma chopping frequency setting the oscillation circuit is built into in ic, and the chopping frequency of the constant current control can be switched by setting serial data 0110, d4, d5, and ***. data[4] data[5] chopping frequency 0 0 390khz 1 0 195khz 0 1 570khz 1 1 285khz no.a1626-9/28
LV8048CS excitation mode setting this section presents the timing charts for each excitation mode. two-phase excitation timing chart (%) 100 0 -100 100 0 -100 (%) i1 i2 clk1 or clk2/pwm or clk3/ena6 0% 100% -100% -100% 0% 100% position number channel 1(channel 3) current channel 2(channel 4) current no.a1626-10/28
LV8048CS 1-2 phase (full torque) excitation timing chart (%) 100 0 -100 -100 100 0 (%) i1 i2 clk1 or clk2/pwm clk3/ena6 0% 100% -100% -100% 0% 100% position number channel 1(channel 3 or channel 5) current channel 2(channel 4 or channel 6) current no.a1626-11/28
LV8048CS 1-2 phase excitation timing chart (%) 100 0 -100 -100 100 0 (%) i1 i2 clk1 or clk2/pwm 0% 100% position number channel 1(channel 3) current channel 2(channel 4) current -100% 100% -100% 0% no.a1626-12/28
LV8048CS 128-division microstep timing chart ichi of the motor also similarly moves 128-division microstep and 25 6-division microstep at the time of each standing up of clk. clk1 or clk2/pwm (%) 100 0 -100 i1 0 i2 -100 (%) 100 1 2 3 4 5 6 7 8 clk1 or clk2/pwm (128) (%) 100 -100 (%) 100 i1 i2 0 -100 expansion position number no.a1626-13/28
LV8048CS 256-division microstep timing chart clk1 or clk2/pwm (%) 100 0 -100 i1 0 i2 -100 (%) 100 1 clk1 or clk2/pwm (256) (%) 100 -100 (%) 100 i1 i2 0 -100 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 expansion position number no.a1626-14/28
LV8048CS operation when excitation mode of operation is changed chenge to microstep(256-division or 128-division) after the change, it moves to the following position of microstep by the first pulse when changing to microstep(256-division or 128-divi sion) from each excitation mode. 100.0 66.7 33.3 0.0 33.3 66.7 100.0 (two aspect, 1-2 aspect full torque) channel 1 aspect current ratio(%) channel 2 aspect current ratio(%) before the change of the excitation mode step position of excitation mode excitation mode position 256-division microstep 128-division microstep 64 62 63 to 33 62 to 32 32 30 31 to 1 30 to 0 256-division microstep 0 - 2 64 63 63 to 33 62 to 32 32 31 31 to 1 30 to 0 128-division microstep 0 - 1 64 63 62 32 31 30 1-2 phase 0 - 1 - 2 64 63 62 32? 31 30 1-2 phase full torque 0 - 1 - 2 two phase 32? 31 30 no.a1626-15/28
LV8048CS change to 1-2 aspect excitation (1-2 aspect excitation full torque) it moves to 32( 32') by the first pulse after the change when changing to 1-2 aspect excitation (1-2 aspect exciting full torque) from each excitation mode, and it shifts to 1-2 aspect excitation (1-2 aspect exciting full torque) afterwards. however, after the change, it moves to the following position of 1-2 aspect excitation (1-2 aspect exciting full torque) by the first pulse when the position of the previous state of the change is 32( 32'). change to two aspect excitation it moves to 32 'by the first pulse after the ch ange when changing from 1ch to two aspect excitation from each excitation mode for 4ch, and it moves to the following position of two aspect excitation afterwards. however, after the change, it moves to the following position by the first pulse for 5ch and 6ch. 100.0 66.7 33.3 0.0 33.3 66.7 100.0 channel 1 aspect current ratio(%) channel 2 aspect current ratio(%) (two aspect, 1-2 aspect full torque) before the change of the excitation mode step position of excitation mode excitation mode position 1-2 phase 1-2 phase full torque two phase 64 32 32? 32? 63 to 33 32 32? 32? 32 0 0 32? 31 to 1 32 32? 32? 256-division microstep 0 - 32 - 32? - 32? 64 32 32? 32? 63 to 33 32 32? 32? 32 0 0 32? 31 to 1 32 32? 32? 128-division microstep 0 - 32 - 32? - 32? 64 32? 32? 32 0 32? 1-2 phase 0 - 32? - 32? 64 32 32?( 32?) 32? 0 32?(- 32?) 1-2 phase full torque 0 - 32 - 32? (- 32?) no.a1626-16/28 two phase 32? 0 0( 0) *()in the inside, for 5ch and 6ch
LV8048CS sample timing chart for the excitation direction setting the excitation direction setting sets the excitation (rotation) direction of the stepping motor. with the cw (clockwise) setting, the phase of the channel 2 current is delayed from that of the channel 1 current by 90. with the ccw (counterclockwise) setting, the phase of the cha nnel 2 current leads that of the channel 1 current by 90. the same applies for channel 3, 4, 5 and 6 drive. (8) (8) (7) (1) (3) (2) (5) (3) (4) (4) (1) (2) cw (clockwise) excitation direction (clk2/pwm) or clk3/ena6) clk1 channel 2 output channel 1 output (position number) ccw (counterclockwise) no.a1626-17/28
LV8048CS step/hold operation overview logic clk (external) internal clk internal logic step/hold setting signal logic sample timing chart for the step/hold setting when the step/hold data is set to the hold state, the state of the external clock signal (clk) at that time is latched and held as the internal clock signal. at the timing with which step/hold is set to the hold state for the first time in the figure below, the internal clock signal will be held at the low level because the external clock (clk) was at the low level. in contrast, at the timing with which step/hold is set to the hold state for the second time, the internal clock signal w ill be held at the high level because the external clock (clk) wa s at the high level. when step/hold is set to the clear state, the internal cloc k is synchronized with the external clock (clk). the output holds the state it was in at the point step/hold is set to the hold state, and advances on the next clock signal rising edge after step/hold is set to the clear state. as long as step/hold is in the hold state, the position number does not advance even if an external clock (clk) signal is applied. (8) (8) (7) (7) (7) (1) (6) (7) (5) (3) (3) (3) (3) (4) (1) (2) clk (external) internal clock step/hold clear hold clear clear hold hold state hold state held at the low level held at the high level (position number) (%) 100 0 100 -100 -100 0 (%) i1 i2 no.a1626-18/28
LV8048CS sample timing chart for the counter reset setting when the counter reset setting is set to the reset state, the ou tput goes to the initial state on the rising edge of the stb signal. then, when the counter reset setting is set to the norm al operation (cleared) state, the output begins to advance the position number on the rising edge of the clk signal following the rise of the stb signal. (8) (1) (8) (2) (4)(3) (6) (7) (5) (3) (4) (1) (2) clk channel 1 output channel 2 output (position number) counter reset normal operation reset normal operation initial state (5) (8) (8) (8) (8) sample timing chart for the output enable setting when the output enable setting is set to the output off state, the outputs are turned off and set to the high-impedance state on the rising ed ge of the stb signal. note, however, that since the internal clock continues to operate, the position number advances as long as a clock signal (clk) is input. therefore, when the output enable setting is next set to the output on (c leared) state, the output is turned on at the stb signal rising edge and the output leve ls at that time will be those for the position number to which the state has advanced due to the clk signal input. (8) (8) (8) (7) (7) (1) (3)(2) (5) (5) (6) (6) (4) (3) (4) (1) (2) output on output off outputs are in the high-impedance state output on clk channel 1 output channel 2 output (position number) output enable no.a1626-19/28
LV8048CS no.a1626-20/28 dc motor and voice coil motor drive methods (channel 3, 4) when channel 3 or channel 4 is used to drive a dc or voice coil motor, the drive polarity is set with the serial data. setting procedure (1) set pwm signal input(channel 3 to 4) to clk2/pwm select with the serial data. this sets up the signal input from the clk2/pwm pin to be accepted as a pw m signal for channel 3 or channel 4. ( it doesn't accept as clk signal.) (2) if the output is to be controlled by pwm control, set up pwm mode and pwm signal allocation with the serial data. (3) set the drive polarity for each channel with the serial data. (4) if the output is to be controlled by pwm control, input the clk2/pwm signal to the pwm pin. the following tables describe th e correspondence between the pwm signal and the output logic. operation in slow decay mode (forward/reverse ? brake) serial input pwm input output d4 d5 d6 d7 clk2/pwm out5 out6 out7 out8 mode 0 0 off off standby mode 1 0 h l out5 out6 0 1 l h out6 out5 1 1 l l brake mode 0 0 off off standby mode 1 0 h l out7 out8 0 1 l h out8 out7 1 1 l l l brake mode 0 0 l l brake mode 1 0 l l brake mode 0 1 l l brake mode 1 1 l l brake mode 0 0 l l brake mode 1 0 l l brake mode 0 1 l l brake mode 1 1 h l l brake mode operation in fast decay mode (forward/reverse ? standby mode) serial input pwm input output d4 d5 d6 d7 clk2/pwm out5 out6 out7 out8 mode 0 0 off off standby mode 1 0 h l out5 out6 0 1 l h out6 out5 1 1 l l brake mode 0 0 off off standby mode 1 0 h l out7 out8 0 1 l h out8 out7 1 1 l l l brake mode 0 0 off off standby mode 1 0 off off standby mode 0 1 off off standby mode 1 1 off off standby mode 0 0 off off standby mode 1 0 off off standby mode 0 1 off off standby mode 1 1 h off off standby mode
LV8048CS no.a1626-21/28 voice coil motor drive methods (channels 5 and 6) when channel 5 or 6 is used to drive a mo tor, such as a voice coil motor, the drive polarity is set using the serial data. the setting procedure for each channel is shown below. [when channel 5 is used] set the drive polarity using the serial data. the signal is output between out9 and out10 when the serial data is set. setup steps the direction where each channel is drive polarity to the serial data. serial input output d4 d5 out9 out10 mode 0 0 off off standby mode 1 0 h l out9 out10 0 1 l h out10 out9 1 1 l l brake mode channel 5 when you control pwm. (1) set clk2/pwm selection to ?pwm signal input(channel 5)? with the serial data. this sets up the signal input fr om the clk2/pwm pin to be accepted as a pwm signal for channel 5. (2) set clk3/ena6 selection to ?ena6 signal input? with the serial data. this sets up the signal input fr om the clk3/ena6 pin to be accepted as a ena signal for channel 6. it comes to be able to set the direction where channel 5 and channel 6 are drive polarity to the serial data. (3) set the drive polarity using the serial data.. the signal is output between out9 an d out10 when the serial data is set. operation in slow decay mode (forward/reverse ? brake) serial input pwm input output d4 d5 clk2/pwm out9 out10 mode 0 0 off off standby mode 1 0 h l out9 out10 0 1 l h out10 out9 1 1 l l l brake mode 0 0 off off standby mode 1 0 l l brake mode 0 1 l l brake mode 1 1 h l l brake mode operation in fast decay mode (forward/reverse ? standby mode) serial input pwm input output d4 d5 clk2/pwm out9 out10 mode 0 0 off off standby mode 1 0 h l out9 out10 0 1 l h out10 out9 1 1 l l l brake mode 0 0 off off standby mode 1 0 off off standby mode 0 1 off off standby mode 1 1 h l l brake mode
LV8048CS no.a1626-22/28 [when channel 6 is used] (1) set clk3/ena6 selection to ?ena6 signal input? with the serial data. this sets up the signal input fr om the clk3/ena6 pin to be accepted as a ena signal for channel 6. it comes to be able to set the direction where channel 5 and channel 6 are drive polarity to the serial data. (3) set the drive polarity using the serial data. the signal is output between out11 and out12 only when ena6 is set to high. (when ena6 is low, the signal output between out11 and out12 is set to off.) ena6 input truth table serial input parallel input output d6 d7 ena5 out11 out12 mode * * l off off standby mode 0 0 off off standby mode 1 0 h l out11 out12 0 1 l h out12 out11 1 1 h l l brake mode constant current control settings (channels 5 and 6) the constant current levels for channels 5 and 6 are set as shown below. the output constant current is set by the constant current refe rence voltage set with the serial data and the resistor (rf) connected between the rf5 and rf6 pins. the following formula can be used to cal culate the output constant current. (output constant current) = (constant current reference voltage) / (value of the resistor rf) reference voltage setting: channel 5 setting(d0 = [0], d1 = [0], d2 = [0], d3 = [1]) channel 6 setting(d0 = [1], d1 = [0], d2 = [0], d3 = [1]) d4 d5 d6 d7 constant current reference voltage 0 0 0 0 0.200v 1 0 0 0 0.170v 0 1 0 0 0.165v 1 1 0 0 0.160v 0 0 1 0 0.155v 1 0 1 0 0.150v 0 1 1 0 0.145v 1 1 1 0 0.140v 0 0 0 1 0.135v 1 0 0 1 0.130v 0 1 0 1 0.125v 1 1 0 1 0.120v 0 0 1 1 0.115v 1 0 1 1 0.110v 0 1 1 1 0.105v 1 1 1 1 0.100v [motor holding current mode] the constant current reference voltages for channels 5 and 6 are switched to one-third levels when the motor holding current is set to on by the serial data. pi1, pi2 output drive method when the pi1 or pi2 output is used to drive a photosensor, the drive on/off state is set using the serial data. hysteresis settings of schmitt buffer the presence or absence of hysteresis in the schmitt buffer outputs b01 and b02 can be set individually with the serial data.
LV8048CS no.a1626-23/28 truth tables serial logic table 1 input channels set pi serial data activation timing d0 d1 d2 d3 d4 d5 d6 d7 d8 setting mode content set notes out1-2 out3-4 out5-6 out7-8 out9-10 out11-12 clk1 clk2 clk3 stb 0 * * * * cw (clockwise) 1 * * * * af excitation direction ccw (counterclockwise) { * 0 * * * clear * 1 * * * af step/hold hold * * 0 * * reset * * 1 * * af counter reset clear * * * 0 * output off * * * 1 * af output enable output on { { { * * * * 0 0 0 0 0 * * * * 1 (dummy data) 0 0 * * * 2-phase excitation 1 0 * * * 1-2 phase excitation (full torque) 0 1 * * * 1-2 phase excitation 1 1 * * * af excitation mode microstep * * 0 * * 256 divisions * * 1 * * microstep division number 128 divisions { { { * * * 0 * * * * 1 * (dummy data) * * * * 0 1 0 0 0 * * * * 1 (dummy data) 0 * * * * clk2 signal input *1 1 * * * * clk2/pwm select pwm signal input *2 * 0 * * * slow decay (forward/reverse ? brake) * 1 * * * pwm mode fast decay (forward/reverse ? standby mode) * * 0 0 off * * 1 0 channel 3 only * * 0 1 channel 4 only * * 0 1 1 channel 3 and 4 0 1 0 0 * * 1 * * pwm signal allocation channel 5 only *2 { { { { 0 * * * * cw (clockwise) 1 * * * * zoom excitation direction ccw (counterclockwise) * 1 * * * clear * 1 * * * zoom step hold hold { * * 0 * * reset * * 1 * * zoom counter reset clear * * * 0 * output off * * * 1 * zoom output enable output on * * * * 0 * * * * 1 (dummy data) *1 { { { 0 0 * * * off 1 0 * * * out5 out6 0 1 * * * out6 out5 1 1 * * * out5-6 drive polarity brake { * * 0 0 * off * * 1 0 * out7 out8 * * 0 1 * out8 out7 * * 1 1 * out7-8 drive polarity brake *2 { { * * * * 0 1 1 0 0 * * * * 1 (dummy data)
LV8048CS no.a1626-24/28 serial logic table 2 input channels set pi serial data activation timing d0 d1 d2 d3 d4 d5 d6 d7 d8 setting mode content set notes out1-2 out3-4 out5-6 out7-8 out9-10 out11-12 clk1 clk2 clk3 stb 0 * * * * cw (clockwise) 1 * * * * sh excitation direction ccw (counterclockwise) * 0 * * * 2-phase excitation * 1 * * * sh excitation mode 1-2 phase excitation { * * 0 * * clear * * 1 * * sh step/hold hold * * * 0 * reset * * * 1 * sh counter reset clear * * * * 0 output off * * * * 1 sh output enable output on *3 { { { 0 0 * * * off 1 0 * * * out9 out10 0 1 * * * out10 out9 1 1 * * * out9-10 drive polarity brake { * * 0 0 * off * * 1 0 * out11 out12 * * 0 1 * out12 out11 * * 1 1 * out11-12 drive polarity brake *4 { { * * * * 0 1 0 1 0 * * * * 1 (dummy data) 0 0 * * * 390khz 1 0 * * * 195khz 0 1 * * * 570khz 1 1 * * * chopping frequency setting 285khz * * 0 0 * 100%(0.2v) * * 1 0 * 70%(0.140v) * * 0 1 * 50%(0.1v) * * 1 1 * chopping current standard voltage select 30%(0.060v) { { { { * * * * 0 clk3 signal input 9 *3 { 0 1 1 0 * * * * 1 clk3/ena6 select ena6 signal input 9 *4 { { 0 0 * * * 2-phase excitation 1 0 * * * 1-2 phase excitation (full torque) 0 1 * * * 1-2 phase excitation 1 1 * * * zoom excitation mode microstep * * 0 * * 256 divisions * * 1 * * number of partitions to microstep 128 divisions { { { * * * 0 * * * * 1 * (dummy data) * * * * 0 1 1 1 0 * * * * 1 (dummy data)
LV8048CS no.a1626-25/28 serial logic table 3 input channels set pi serial data activation timing d0 d1 d2 d3 d4 d5 d6 d7 d 8 setting mode content set notes out1-2 out3-4 out5-6 out7-8 out9-10 out11-12 clk1 clk2 clk3 stb 0 0 0 0 * 0.200v 1 0 0 0 * 0.170v 0 1 0 0 * 0.165v 1 1 0 0 * 0.160v 0 0 1 0 * 0.155v 1 0 1 0 * 0.150v 0 1 1 0 * 0.145v 1 1 1 0 * 0.140v 0 0 0 1 * 0.135v 1 0 0 1 * 0.130v 0 1 0 1 * 0.125v 1 1 0 1 * 0.120v 0 0 1 1 * 0.115v 1 0 1 1 * 0.110v 0 1 1 1 * 0.105v 1 1 1 1 * out9-10 constant current reference voltage 0.100v { { * * * * 0 0 0 0 1 * * * * 1 (dummy data) 0 0 0 0 * 0.200v 1 0 0 0 * 0.170v 0 1 0 0 * 0.165v 1 1 0 0 * 0.160v 0 0 1 0 * 0.155v 1 0 1 0 * 0.150v 0 1 1 0 * 0.145v 1 1 1 0 * 0.140v 0 0 0 1 * 0.135v 1 0 0 1 * 0.130v 0 1 0 1 * 0.125v 1 1 0 1 * 0.120v 0 0 1 1 * 0.115v 1 0 1 1 * 0.110v 0 1 1 1 * 0.105v 1 1 1 1 * out11-12 constant current reference voltage 0.100v { * * * * 0 off(100%) 1 0 0 1 * * * * 1 maintenance voltage (out9-10/11-12) on(33%) { { { 0 * * * * off 1 * * * * photo senser1 drive on * 0 * * * off * 1 * * * photo senser2 drive on { * * 0 * * not * * 1 * * buffer hysteresis (bi1/bo1) having * * * 0 * not * * * 1 * buffer hysteresis (bi2/bo2) having { * * * * 0 0 1 0 1 * * * * 1 (dummy data)
LV8048CS equivalent circuits pin no. pin name equivalent circuit e4 d6 bo1 bo2 v cc e4 d6 sgnd a6 a7 b7 a3 a4 a5 e1 f1 f2 f3 f4 f5 out1 rf1 out2 out3 rf2 out4 out5 rf3 out6 out7 rf4 out8 a3 a6 a7 a4 b7 a5 vb f3 e1 f5 f2 f1 f4 f6 f7 e7 out11 rf6 out12 f6 f7 e7 vb v cc sgnd c2 b2 d2 b4 b5 b6 data stb sclk clk1 clk2/pwm clk3/ena6 v cc c2 b2 sgnd d2 b4 b5 b6 continued on next page. no.a1626-26/28
LV8048CS continued from preceding page. pin no. pin name equivalent circuit b3 st v cc b3 sgnd b2 a1 a2 out10 rf5 out9 b2 a1 a2 vb v cc sgnd e5 e6 bi1 bi2 v cc e5 e6 sgnd e2 e3 pi1 pi2 e2 e3 sgnd no.a1626-27/28
LV8048CS sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of december, 2009. specifications and inform ation herein are subject to change without notice. ps no.a1626-28/28

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